The invention relates to a power supply protection arrangement of a video display apparatus, for example, a projection television (TV) receiver.
The displayed image in, for example, a direct view TV receiver or in a projection TV receiver having a cathode ray tube (CRT), may suffer from electron beam landing location errors such as geometrical and convergence errors. It is known to correct such errors for a CRT using a dynamic convergence arrangement. The amount of correction may vary dynamically in a given deflection cycle, in accordance with the location of the beam on the display screen.
In one prior art arrangement, to minimize manufacturing costs of a direct view TV receiver model and a projection TV receiver model, both models shared the same chassis. The main deflection circuits were common. Direct view models used about 90% of the chassis. For economic reasons the main chassis power supply was sized for the direct view model and a projection convergence power supply was added on for a projection TV receiver model.
When, as a result of a fault, a supply current exceeds a predetermined value, a threshold level of a protection detector is exceeded and causes the dedicated convergence switch mode power supply to shut down. Trouble shooting convenience requires that the TV receiver show a picture when the convergence circuits have a fault. Thus, the rest of the TV receiver circuits including the deflection circuits remain energized and operational. The convergence dedicated switch mode supply remains turned off until the projection TV receiver is turned off and then on, again, by a user.
In carrying out an inventive feature, a common switch mode power supply energizes the convergence circuits and the rest of the TV receiver circuits. Instead of using the prior art separate power supplies solution, a fast acting latching power supply voltage disconnect arrangement for the convergence circuits is utilized. Such arrangement provides a cost advantage.
FIG. 1 illustrates an example of a prior art power amplifier that drives the convergence winding in a CRT of the projection video display, shown in FIG. 3 of U.S. Pat. No. 4,961,032 in the name of Rodriguez-Cavazos, entitled, Dual Power Source Output Amplifier (the Rodriguez-Cavazos patent). The symbols and reference numerals in FIG. 1 are the same as in FIG. 3 of the Rodriguez-Cavazos patent except that a prime sign (′) is appended to each.
In FIG. 1, an amplifier 50′ comprises a differential amplifier 12′, a buffer 14′ and one output stage 16′. The differential amplifier 12′ is formed by transistors Q1′ and Q2′. An input waveform signal VIN′ is connected to the base of transistor Q1′. The collector of transistor Q1′ is connected to a high voltage supply source of positive polarity voltage +VH′. The emitters of transistors Q1′ and Q2′ are connected together, and through a resistor R1′, to a negative high supply voltage −VH′. A parallel combination of sense resistors R21′ and R22′ are connected to a deflection coil 24′ of a yoke Y1′ and the base of transistor Q2′, for developing the sense voltage VS. A transistor Q11′ converts the output current at the collector of transistor Q2′ into an output voltage across a load resistor R18′. Diodes D8′, D9′, D10′ and D11′ establish a biasing voltage for the buffer stage 14′, which includes transistors Q9′ and Q10′. The emitters of transistors Q9′ and Q10′ of the buffer stage drive the bases of transistors Q4′ and Q5′, respectively, through resistors R13′ and R14′, respectively. Transistors Q4′ and Q5′ form class B output stage 16′. The emitters of transistors Q4′ and Q5′ are connected to resistors R7′ and R8′, respectively. The output voltage signal of the amplifier is generated at the junction of resistors R7′ and R8′, which is connected to the coil 24′ of convergence yoke Y1′.
Output stage 16′ provides high current. It needs to provide a high voltage drive, during horizontal retrace, and a low voltage drive, outside horizontal retrace. Output stage 16′ compares dynamically varying input signal VIN′ to sense voltage VS developed across current sense resistors R21′ and R22′ that are coupled in series with the convergence winding. Output stage 16′ generates the necessary current to minimize any difference between the varying input signal VIN′ and sense voltage VS′.
If positive polarity voltage +VH′ is turned off and, simultaneously, negative voltage supply −VH′ is turned on, during a power-up or start-up interval, transistors Q10′ and Q5′ will turn on at the limit Consequently, a current IY1′ in convergence yoke Y1′ having an excessive magnitude flows also in sense resistors R21′ and R22′ that could damage them. Even a short-term overstress may cause an unacceptable sense resistor value change. A sense resistor value change causes an uncompensated change in convergence correction gain that distorts the picture.
In a power supply embodying an inventive feature, a positive polarity voltage that is analogous to voltage +VH′ is turned on prior to turning on of negative voltage supply that is analogous to voltage −VH′, during the power-up or start-up interval. Furthermore, a power supply circuit breaking protection is employed that prevents excessive current in the sense resistors, as a result of a failure in the feedback loop.